The present invention relates to a method for fabricating metal interconnections used for flat panel displays such as liquid crystal displays (LCD), plasma display panels (PDP), electrochromic displays (ECD) and electroluminescent displays (ELD), or flat panel sensors such as X-ray imaging devices.
In a flat panel display typified by LCD, normally, display material such as liquid crystals or discharge gas is sandwiched between a pair of insulating substrates, and electrical interconnection lines are arrayed on at least one of the insulating substrates, where a voltage is applied to the display material via the electrical lines.
For example, in the case of an active matrix drive type LCD, a plurality of gate electrodes and a plurality of data electrodes are provided in a matrix shape on an active matrix substrate, which is one of the pair of insulating substrates between which the display material is sandwiched. At intersections of these gate electrodes and data electrodes, thin film transistors (TFT) and pixel electrodes are provided every intersection. Normally, these gate electrodes and data electrodes are made of metal material such as tantalum (Ta), aluminum (Al) or molybdenum (Mo), and deposited by dry deposition process such as sputtering process.
In such flat panel displays, in an attempt to implement larger areas and higher definitions, increased drive frequencies would cause the resistance of the electrical lines as well as the parasitic capacitance to increase. As a result of this, delay of driving signals would come up as a large problem.
Thus, in order to solve the problem of the delay of driving signals, there has been made an attempt to use Cu (copper, bulk resistivity: 1.7 xcexcxcexa9xc2x7cm) having lower electrical resistance as the interconnection material, instead of Al (bulk resistivity: 2.7 xcexcxcexa9xc2x7cm), xcex1-Ta (bulk resistivity: 13.1 xcexcxcexa9xc2x7cm) or Mo (bulk resistivity: 5.8 xcexcxcexa9xc2x7cm), which are conventional interconnection materials. For example, xe2x80x9cLow Resistance Copper Address Line for TFT-LCDxe2x80x9d (Japan Display ""89, pp. 498-501) discloses discussion results on a case of using Cu as the gate electrode material of TFT-LCD (thin film transistor liquid crystal display). According to this literature, it is pointed out that because a Cu film deposited by sputtering process is poor in adhesion to the ground glass substrate, a ground metal film of Ta or the like needs to be interveniently provided between the ground glass substrate and the Cu film in order to enhance the adhesion to the ground glass substrate.
However, in the case of the interconnection structure shown in the above literature, separate deposition processes are involved for the Cu film and the ground metal film of Ta or the like, causing a process increase and leading to a cost increase, as a disadvantage.
Also, separate etching processes are involved for the Cu film and the ground metal film of Ta or the like, causing a process increase and leading to a cost increase, as a disadvantage.
An object of the present invention is to provide a method for fabricating metal interconnections of low resistance, the method consisting of only wet deposition process and involving less etching process.
In order to achieve the above object, in a first aspect of the invention, there is provided a method for fabricating metal interconnections, comprising: a first step for depositing a ground metal film on an insulating substrate by electroless plating; a second step for forming a resist in a specified pattern on the ground metal film; a third step for depositing a noble metal film by electroless plating in a region where the resist is not formed and where the ground metal film is exposed; a fourth step for removing the resist; a fifth step for removing, by etching, the ground metal film exposed by the removal of the resist; and a sixth step for forming a metal film by electroplating or electroless plating selectively on the noble metal film.
In a second aspect of the invention, there is provided a method for fabricating metal interconnections, comprising: a first step for depositing a ground metal film on an insulating substrate by electroless plating; a second step for forming a resist in a specified pattern on the ground metal film; a third step for depositing a noble metal film by electroless plating in a region where the resist is not formed and where the ground metal film is exposed; a fourth step for forming a metal film by electroplating or electroless plating selectively on the noble metal film; a fifth step for removing the resist; and a sixth step for removing, by etching, the ground metal film exposed by the removal of the resist.
In a third aspect of the invention, there is provided a method for fabricating metal interconnections, comprising: a first step for depositing a ground metal film on an insulating substrate by electroless plating; a second step for forming a resist in a specified pattern on the ground metal film; a third step for removing, by etching, the ground metal film present in a region where the resist is not formed; a fourth step for removing the resist; a fifth step for depositing a noble metal film by electroless plating selectively on the ground metal film exposed by the removal of the resist; and a sixth step for forming a metal film by electroplating or electroless plating selectively on the noble metal film.
In a fourth aspect of the invention, there is provided a method for fabricating metal interconnections, comprising: a first step for applying and forming a plating catalyst precursor on an insulating substrate; a second step for exposing to light the plating catalyst precursor in a specified pattern to form a plating catalyst into the specified pattern; a third step for removing the plating catalyst precursor in a region where the plating catalyst precursor is not exposed to light; a fourth step for depositing a ground metal film by electroless plating selectively on the patterned plating catalyst; a fifth step for depositing a noble metal film by electroless plating selectively on the ground metal film; and a sixth step for forming a metal film by electroplating or electroless plating selectively on the noble metal film.
According to the first to fourth aspects of the invention, the ground metal film, the noble metals and the metal films are all deposited by plating technique, which is a wet deposition technique. The wet deposition technique allows the equipment cost to be reduced because of its never using any evacuation system, as compared with the dry deposition technique.
Also, the wet deposition technique, in which film deposition is carried out in an aqueous solution, involves a deposition temperature as low as 100xc2x0 C. or lower, thus reducing the energy consumption associated with film deposition, as compared with the dry deposition technique.
Further, the wet deposition technique, even with a large-size (large-area) substrate, involves less restrictions on equipment, as compared with the dry deposition technique, thus capable of easily achieving large-sized film deposition.
Also, according to the first to fourth aspects of the invention, the formation of resist pattern using photolithography has to be done only once in the second step, and the metal film etching also has to be done in the fifth step in the first aspect, the sixth step in the second aspect, or the third step in the third aspect. Further, in the fourth aspect of the invention, the metal film etching process is not necessary. Therefore, despite a stacked interconnection structure of a ground metal film, a noble metal film and a metal film, the fabrication process becomes simple, resulting in inexpensive interconnections.
Further, according to the first to fourth aspects of the invention, since a ground metal film superior in adhesion to the insulating substrate is interveniently provided between the insulating substrate and the metal film, the metal film can ensure a high adhesion to the insulating substrate.
Also, since a noble metal film of low electrical resistance is interveniently provided between the metal film and the ground metal film, current density required for plating can be uniformly distributed during the deposition of the metal film by electroplating. Therefore, a metal film uniform in film thickness can be obtained even with a large-area substrate.
Still further, according to the first to fourth aspects of the invention, since a noble metal film or metal film which is chemically stable and hard to pattern by etching is patterned by plating, an interconnection configuration can be easily formed.
In an embodiment of the first or second aspect of the invention, the electroless plating of the noble metal film in the third step is substitute plating for substituting the noble metal film for a surface of the ground metal film deposited in the first step.
In an embodiment of the third or fourth aspect of the invention, the electroless plating of the noble metal film in the fifth step is substitute plating for substituting the noble metal film for a surface of the ground metal film deposited in the first or fourth step.
According to these embodiments, since the electroless plating of the noble metal film is substitute plating for substituting the noble metal film for the surface of the ground metal film, the thickness of metallic deposit does not substantially vary before and after the electroless plating of the noble metal film. Further, since substitute reaction of the ground metal film and the noble metal film is used, there is no need for process of giving a catalyst such as Pd onto the ground metal film.
In an embodiment of the first aspect of the invention, in the fifth step of removing the ground metal film by etching, the noble metal film formed in the third step is used as an etching mask.
According to this embodiment, since the noble metal film formed in the third step and being very chemically stable is used as an etching mask without using photolithography process, the ground metal film can be patterned in self alignment.
In an embodiment of the second aspect of the invention, in the sixth step of removing the ground metal film by etching, the metal film deposited in the fourth step is used as an etching mask.
Therefore, according to this embodiment, the ground metal film can be patterned in self alignment by using the metal film as an etching mask without using photolithography process, and by selecting an etchant having a low etching rate for the metal film and a high etching rate for the ground metal film.
In an embodiment of the first to fourth aspects of the invention, the method for fabricating metal interconnections further comprises a seventh step for forming a surface metal film on the metal film in addition to the first to sixth steps.
According to this embodiment, since a surface metal film is formed on the metal film in the seventh step, the metal film is protected without being exposed to the atmosphere, so that the metal film can be prevented from oxidation.
In an embodiment of the first to fourth aspects of the invention, the ground metal film is formed of nickel.
According to this embodiment, since the ground metal film is formed of nickel, a high adhesion of the metal film to a glass substrate, which is typical of the insulating substrate, can be ensured.
In an embodiment of the first to fourth aspects of the invention, the noble metal film is formed of gold.
According to this embodiment, since the noble metal film is formed of gold, substitute plating for the ground metal film of nickel can be easy to achieve.
In an embodiment of the first to fourth aspects of the invention, the metal film is formed of copper.
According to this embodiment, inexpensive low-resistivity interconnections which are stable even with large current density can be implemented since the metal film is formed of copper, which is low in resistivity, long in life to electromigration and low in price.